Cache memory - PDFSEARCH.IO - Document Search Engine

Cache memory
Results: 1188

#	Item
561	Digital Semiconductor[removed]Core Logic Chipset Technical Reference Manual Order Number: EC–QUQJA–TE Revision/Update Information: Add to Reading List Source URL: download.majix.org Language: English - Date: 2013-01-10 05:04:28 Conventional PCI PCI configuration space PCI Express Memory-mapped I/O CPU cache Cell Translation lookaside buffer Direct memory access IOMMU Computer hardware Computer buses Computing
562	Profile-Based Energy Reduction for High-Performance Processors Michael Huang, Jose Renau, and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu ABSTRACT Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2001-12-10 19:52:52 Computer architecture Profilers Software optimization CPU cache Cache Computer memory Profiling Program optimization Microarchitecture Computing Computer hardware Central processing unit
563	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
564	OmniOrder: Directory-Based Conflict Serialization of Transactions ∗ Xuehai Qian † University of California, Berkeley Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-04-19 12:44:14 Computer hardware Computer memory CPU cache MESI protocol MSI protocol Cache Transactional memory Parallel computing Cache coherency Computing Concurrent computing
565	CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2004-12-21 00:54:20 Central processing unit Runahead CPU cache Microprocessors Branch predictor Memory-level parallelism Microarchitecture Instruction window Hardware scout Computer architecture Computer hardware Computer engineering
566	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection∗ Abdullah Muzahid, Norimasa Otsuki† , and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-10-23 11:07:53 Data Transaction processing Computer memory Parallel computing Linearizability CPU cache I1 Cache Q Computing Data management Concurrency control
567	The Stanford Hydra CMP Lance Hammond, Ben Hubbert, Michael Siu, Manohar Prabhu, Michael Chen, Maciek Kozyrczak, and Kunle Olukotun Computer Systems Laboratory Stanford University http://www-hydra.stanford.edu Add to Reading List Source URL: www-hydra.stanford.edu Language: English* - Date: 1999-11-05 21:09:40 Computer architecture CPU cache Cache Central processing unit Multi-core processor Parallel computing Direct memory access Harvard architecture Computer hardware Computing Computer memory
568	USING AN ADAPTIVE HPC RUNTIME SYSTEM TO RECONFIGURE THE CACHE HIERARCHY SC’14, Nov. 20, 2014 Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-12-19 19:14:48 Central processing unit Ø Slashed zero Numbers Information Computer memory Cache CPU cache
569	SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization ∗ James Tuck‡ ‡ NC State University Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-20 21:14:12 Software optimization Software engineering Data types Primitive types Memoization CPU cache Lookup table Memory disambiguation Pointer Computing Computer programming Computer performance
570	BulkCommit: Scalable and Fast Commit of Atomic Blocks ∗ in a Lazy Multiprocessor Environment † Xuehai Qian , Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-10-25 19:56:50 Computer file formats Graphics file formats Cache coherency Chunk CPU cache MESI protocol ANIM Parallel computing C dynamic memory allocation Computing Computer memory Computer hardware

UPDATE